2.2.2.4 Watchdog Configuration
The ATA8510/15 integrates a watchdog timer that prevents the system from stalling. The time-out period can be configured in eight steps between 1 ms and 268s. For more information, see Table 3-88. The reference clock for the watchdog timer is the SRC; therefore, the watchdog timer also works in all sleep modes.
If enabled, the watchdog timer has to be reset by a watchdog reset (WDR) AVR instruction before a time-out occurs. Otherwise, a full system reset is triggered. The WDR is done by the firmware during the main loop. In PollingMode, the main loop has a low priority, therefore, the time-out value of the watchdog must be at least twice as long as the active period in PollingMode. If PollingMode is configured with an AVR sleep mode, the WDR is disabled during the sleep period. As a result, the time-out value of the watchdog must be set longer than the sleep period in PollingMode. If the system runs in a receive mode, the WDR is not executed as long as the system is waiting for wake check ok (WCO) signalization and the time-out value of the watchdog has to be set longer than the maximum demodulator/WCO time-out.
The watchdog can be enabled by setting the eepWdtConf.confWDTCR.WDE variable to
‘1’. The time-out period is coded in the 3-bit variable
eepWdtConf.confWDTCR.WDPS[2:0].
For more information, see EEPromWDTimer eepWdtConf.
| Address | Name | Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
|---|---|---|---|---|---|---|---|---|---|
| 0x0093 | confWDTCR | — | — | — | WDCE | WDE | WDPS[2:0] | ||
|
Note: The watchdog enable bit is
overruled by the watchdog timer always on (WDTON) fuse. If the fuse is programmed,
the watchdog timer cannot be disabled via the EEPROM.
| |||||||||
A detailed description of the watchdog timer hardware IP is given in Timer0 – Watchdog/Interval Timer.