3.10.7.1 Timer0 – Watchdog/Interval Timer

Timer0 is a watchdog/interval timer that can be used to generate periodical interrupts and as a prescaler for the watchdog function. This timer also runs during UHF reception; therefore, it is designed to avoid harmonics and noise generation.

The watchdog/interval is clocked from a calibrated on-chip slow RC (SRC) oscillator with a nominal frequency of f_SRC = 125 kHz. The oscillator is described in Clock Sources.

The SRC and the Timer0 can work together as an ultra-low power watchdog/interval timer stage.

Timer0 consists of a programmable 24-stage divider that is driven by CLK_SRC. The timer output signal (CLK_T0) can be used as a source for the Timer0 interrupt. The interrupt is maskable via the T0IE bit and the interval for the timer output can be adjusted as shown in T0CR via the T0PS[2:0] bits in the Timer0 control register T0CR.

The timer starts running automatically after any power-on reset. If the watchdog function is not activated, the timer can be restarted by writing a logic ‘1’ to the T0PR bit in the T0CR register.

Timer0 can also be used as a watchdog timer to prevent system stalling. The watchdog divider is a 3-bit counter that is supplied by a separate output clock (CLKWD) of Timer0 and generates a system reset when the 3-bit counter overflows. To avoid this, the 3-bit counter must be reset before it overflows. The application software has to accomplish this by executing the WATCHDOG RESET (WDR) instruction to restart the watchdog counter before the time-out value is reached. The watchdog counter is also reset when it is disabled and when a chip reset occurs. Eight different clock cycle periods can be selected to determine the reset period. If the reset period expires without another watchdog reset, the microcontroller is reset and executes from the reset vector. By controlling the watchdog timer prescaler, the watchdog reset interval can be adjusted, as shown in WDPS, via the WDPS[2:0] bits in the Timer0 watchdog control register WDTCR.

To prevent unintentional disabling of the watchdog or unintentional change of the time-out period, two different safety levels can be selected by the fuse WDTON, as shown in the following table.