3.10.12.1 Program and Data Memory Lock Bits
The ATA8510/15 provides 6 lock bits which can be
left unprogrammed (‘1’) or can be programmed (‘0’) to obtain
the additional security listed in the Table 3-111. The lock bits can only
be erased to ‘1’ with the “chip erase” command.
The program memory can be read out via the debugWIRE interface when the DWEN fuse is programmed, even if the lock bits are set. Thus, when lock bit security is required, debugWIRE must always be disabled by clearing the DWEN fuse.
|
Bit No |
Lock Bit Byte |
Description |
Default Value |
|---|---|---|---|
|
7 | — | — |
|
|
6 | — | — |
|
|
5 |
BLB12 |
Boot lock bit |
|
|
4 |
BLB11 |
Boot lock bit |
|
|
3 |
BLB02 |
Boot lock bit |
|
|
2 |
BLB01 |
Boot lock bit |
|
|
1 |
LB2 |
Lock bit |
|
|
0 |
LB1 |
Lock bit |
|
|
Note: ‘
1’ means
unprogrammed, ‘0’ means programmed | |||
|
Memory Lock Bits (1)(2) |
Description | ||
|---|---|---|---|
|
LB Mode |
LB2 |
LB1 | — |
|
1 |
|
|
No memory lock features enabled. |
|
2 |
|
|
Further programming of Flash and EEPROM is disabled in HVSP and ISP mode. The fuse bits are locked in both, HVSP and ISP mode. DebugWire is disabled. |
|
3 |
|
|
Further programming and verification of Flash and EEPROM is disabled in HVSP and ISP mode. The fuse bits are locked in both, HVSP and ISP mode. DebugWire is disabled. |
|
4 |
|
|
Reserved. |
|
BLB0 Mode |
BLB02 |
BLB01 | — |
|
1 |
|
|
No restrictions for SPM or LPM accessing the application section. |
|
2 |
|
|
SPM is not allowed to write to the application section. |
|
3 |
|
|
SPM is not allowed to write to the application section: LPM executing from the boot loader section is not allowed to read from the application section. If interrupt vectors are placed in the boot loader section, interrupts are disabled while executing from the application section. |
|
4 |
|
|
LPM executing from the boot loader section is not allowed to read from the application section. If interrupt vectors are placed in the boot loader section, interrupts are disabled while executing from the application section. |
|
BLB1 Mode |
BLB12 |
BLB11 | — |
|
1 |
|
|
No restrictions for SPM or LPM accessing the boot loader section. |
|
2 |
|
|
SPM is not allowed to write to the boot loader section. |
|
3 |
|
|
SPM is not allowed to write to the boot loader section; LPM executing from the application section is not allowed to read from the boot loader section. If interrupt vectors are placed in the application section, interrupts are disabled while executing from the boot loader section. |
|
4 |
|
|
LPM executing from the application section is not allowed to read from the boot loader section. If interrupt vectors are placed in the application section, interrupts are disabled while executing from the boot loader section. |
|
Note:
1. Program fuse bits before programming LB1 and LB2. 2. ‘ | |||