3.5.2.7.4 GACDIVL – Gauss Clock Divider, Low Byte

Name:	GACDIVL
Offset:	0x062
Reset:	0x00


Bit	7	6	5	4	3	2	1	0
	GACDIV[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bits 7:0 – GACDIV[7:0] Gauss Clock Divider

Least significant bits 7..0 of the Gauss clock divider value. The entire 13-bit GACDIV word in the GACDIVL and GACDIVH registers can be calculated with the following formula:

G A C D I V = r o u n d (\frac{{C L K}_{X T O}}{{S R}_{a p p} \times 12}) ......(44)

where CLK_XTO is the crystal oscillator frequency in Hz and SR_app is the target symbol rate of the application in symbols/s which is equal to the NRZ-coded data rate and twice the bit rate in Manchester mode. The result has to be rounded to the nearest integer value. Modifying this register during transmit operation can lead to unpredictable results.