3.5.2.7.3 FSFCR – Frequency Synthesizer Filter Control Register

Name:	FSFCR
Offset:	0x061
Reset:	0x00


Bit	7	6	5	4	3	2	1	0
	ASDIV[3:0]						BTSEL[1:0]
Access	R/W	R/W	R/W	R/W	R	R	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bits 7:4 – ASDIV[3:0] ASK Shaping Divider

The ASK shaping divider determines the step width of the ASK shaping curve. 2_ASDIV determines the number of XTO clock cycles between two steps. ASDIV must, therefore, be set according to the following formula:

t_{r i s e / f a l l} = \frac{1}{f_{X T O}} \times 7 \times 2^{A S D I V} ......(43)

where,

t_rise/fall: Overall rise time or fall time in s (including all seven shaping steps)
f_XTO: XTO frequency in Hz

Bit 3 – Reserved Bit

This bit always returns ‘0’ when read.

Bit 2 – Reserved Bit

This bit always returns ‘0’ when read.

Bits 1:0 – BTSEL[1:0] Gauss Filter BT (Bit Time Bandwidth Product) Selection

Writing this register during transmit operation can lead to unpredictable results.


BTSEL		Description
`0`	`0`	BT = 2
`0`	`1`	BT = 1.5
`1`	`0`	BT = 1
`1`	`1`	BT = 0.5