3.5.2.7.5 GACDIVH – Gauss
Clock Divider, High Byte
Name:
GACDIVH
Offset:
0x063
Reset:
0x00
Bit
7
6
5
4
3
2
1
0
GACDIV [12:8]
Access
R
R
R
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit 7 – Reserved Bit
This bit always returns
‘0’ when read.
Bit 6 – Reserved Bit
This bit is reserved and read
as ‘0’.
Bit 5 – Reserved Bit
This bit is reserved and read
as ‘0’.
Bits 4:0 – GACDIV [12:8] Gauss Clock
Divider
Most significant bits 12..8 of
the Gauss clock divider value. Calculation of the value is explained in the GACDIVL
register description. Modifying this register during transmit operation can lead to
unpredictable results.
The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.
