3.5.2.7.8 FFREQ1H – Fractional
Frequency 1 Setting, High Byte
| Name: | FFREQ1H |
| Offset: | 0x066 |
| Reset: | 0x00 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| | | | | | | | FFREQ1H[1:0] | |
| Access | R | R | R | R | R | R | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit 7 – Reserved Bit
This bit always returns
‘0’ when read.
Bit 6 – Reserved Bit
This bit is reserved and read
as ‘0’.
Bit 5 – Reserved Bit
This bit is reserved and read
as ‘0’.
Bit 4 – Reserved Bit
This bit is reserved and read
as ‘0’.
Bit 3 – Reserved Bit
This bit is reserved and read
as ‘0’.
Bit 2 – Reserved Bit
This bit is reserved and read
as ‘0’.
Bits 1:0 – FFREQ1H[1:0] Fractional
Frequency 1 Setting, High Byte
Most significant bits of the
18-bit fractional divider setting 1. The fractional-N PLL output frequency as a
function of settings is described in Fractional-N Divider and SDM
