3.10.5.1.2 PRR0 – Power Reduction Register 0

This register allows a fine-grained clock control. Clocks for various I/O modules can be turned off by setting the corresponding flag to “high”. Therefore, the power consumption of these modules is reduced when they are not needed. All modules except the SPI are disabled by default and they must be enabled if required.
Name: PRR0
Offset: 0x001
Reset: 0x00

Bit 76543210 
 PRCOPRVMPRCRCPRTXDCPRRXDCPRSPI 
Access RRRR/WR/WR/WR/WR/W 
Reset 00111111 

Bit 7 –  Reserved Bit

This bit is reserved and reads as ‘0’.

Bit 6 –  Reserved Bit

This bit is reserved and reads as ‘0’.

Bit 5 – PRCO Power Reduction Clock Output

Writing a logic ‘1’ to this bit stops the clock and shuts down the clock output module. When waking up, the module must be reinitialized to ensure proper operation.

Bit 4 – PRVM Power Reduction Voltage Monitor

Writing a logic ‘1’ to this bit stops the clock to the stage and shuts down the voltage monitor module. When waking up, the module must be reinitialized to ensure proper operation.

Bit 3 – PRCRC Power Reduction CRC

Writing a logic ‘1’ to this bit stops the clock to the stage and shuts down the CRC module. When waking up, the module must be reinitialized to ensure proper operation.

Bit 2 – PRTXDC Power Reduction Transmit DSP Control

Writing a logic ‘1’ to this bit stops the clock and shuts down the transmit DSP control module. When waking up, the module must be reinitialized to ensure proper operation.

Bit 1 – PRRXDC Power Reduction Receive DSP Control

Writing a logic ‘1’ to this bit stops the clock and shuts down the receive DSP control module. When waking up, the module must be reinitialized to ensure proper operation.

Bit 0 – PRSPI Power Reduction Serial Peripheral Interface

Writing a logic ‘1’ to this bit stops the clock to the module and shuts down the serial peripheral interface. When waking up, the module must be reinitialized to ensure proper operation.