3.10.5.1.1 SMCR – Sleep
Mode Control Register
| Name: | SMCR |
| Offset: | 0x038 |
| Reset: | 0x00 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| | | | | | SM[2:0] | SE | |
| Access | R | R | R | R | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit 7 – Reserved Bit
This bit is reserved and read
as ‘0’.
Bit 6 – Reserved Bit
This bit is reserved and read
as ‘0’.
Bit 5 – Reserved Bit
This bit is reserved and read
as ‘0’.
Bit 4 – Reserved Bit
This bit is reserved and read
as ‘0’.
Bits 3:1 – SM[2:0] Sleep Mode
Select
These bits select between the
four available sleep modes, as shown in the following table.Table 3-76. Sleep Mode
Selection| SM[2:0] | SleepMode |
|---|
0 | 0 | 0 | Idle |
0 | 0 | 1 | Extended power-save |
0 | 1 | 0 | Power-down |
0 | 1 | 1 | Power-save |
1 | 0 | 0 | Reserved |
1 | 0 | 1 | Reserved |
1 | 1 | 0 | Reserved |
1 | 1 | 1 | Reserved |
Bit 0 – SE Sleep Mode
Enable
The SE bit must be written to
logic ‘1’ to make the MCU enter the sleep mode when the SLEEP
instruction is executed. To avoid the MCU entering the sleep mode unless it is the
programmer’s purpose, it is recommended to write the Sleep Enable (SE) bit to
‘1’ just before the execution of the SLEEP instruction and to
clear it immediately after waking-up.
