3.10.5.1.3 PRR1 – Power Reduction
Register 1
This register allows a
fine-grained clock control. Clocks for various I/O modules can be turned off by setting
the corresponding flag to “high”. Therefore, the power consumption of these modules is
reduced when they are not needed. The modules are disabled by default and they must be
enabled only if required.| Name: | PRR1 |
| Offset: | 0x002 |
| Reset: | 0x00 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| | | | | PRT5 | PRT4 | PRT3 | PRT2 | PRT1 | |
| Access | R | R | R | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | |
Bit 7 – Reserved
Bit
This bit is reserved and reads
as ‘0’.
Bit 6 – Reserved Bit
This bit is reserved and reads
as ‘0’.
Bit 5 – Reserved Bit
This bit is reserved and reads
as ‘0’.
Bit 4 – PRT5 Power Reduction
Timer 5
Writing a logic
‘1’ to this bit stops the clock to the module and shuts down
Timer 5. When waking up, the module must be reinitialized to ensure proper
operation.
Bit 3 – PRT4 Power Reduction
Timer 4
Writing a logic
‘1’ to this bit stops the clock to the module and shuts down
Timer 4. When waking up, the module must be reinitialized to ensure proper
operation.
Bit 2 – PRT3 Power Reduction
Timer 3
Writing a logic
‘1’ to this bit stops the clock to the module and shuts down
Timer 3. When waking up, the module must be reinitialized to ensure proper
operation.
Bit 1 – PRT2 Power Reduction
Timer 2
Writing a logic
‘1’ to this bit stops the clock to the module and shuts down
Timer 2. When waking up, the module must be reinitialized to ensure proper
operation.
Bit 0 – PRT1 Power Reduction
Timer 1
Writing a logic
‘1’ to this bit stops the clock to the module and shuts down
Timer 1. When waking up, the module must be reinitialized to ensure proper
operation.
