3.10.5.1.4 PRR2 – Power Reduction
Register 2
This register allows a
fine-grained clock control. Clocks for various I/O modules can be turned off by setting
the corresponding flag to “high”. Therefore, the power consumption of these modules is
reduced when they are not needed. The modules are disabled by default and they must be
enabled only if required.| Name: | PRR2 |
| Offset: | 0x003 |
| Reset: | 0x00 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| | PRSSM | PRTM | PRRS | PRIDS | PRDF | PRSF | PRXA | PRXB | |
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | |
Bit 7 – PRSSM Power Reduction
Sequencer State Machine
Writing a logic
‘1’ to this bit stops the clock to the module and shuts down
the sequencer state machine. When waking up, the module must be reinitialized to
ensure proper operation.
Bit 6 – PRTM Power Reduction TX
Modulator
Writing a logic
‘1’ to this bit shuts down the TX modulator by stopping the
clock to the module and setting the user interface to its reset values. When waking
up, the module must be reinitialized to ensure proper
operation.
Bit 5 – PRRS Power Reduction
RSSI Buffer
Writing a logic
‘1’ to this bit shuts down the RSSI buffer by stopping the
clock to the module and setting the user interface to its reset values. When waking
up, the module must be reinitialized to ensure proper
operation.
Bit 4 – PRIDS Power Reduction ID
Check
Writing a logic
‘1’ to this bit shuts down the ID check by stopping the clock
to the module and setting the user interface to its reset values. When waking up,
the module must be reinitialized to ensure proper operation.
Bit 3 – PRDF Power Reduction
Data FIFO
Writing a logic
‘1’ to this bit shuts down the data FIFO by stopping the clock
to the module and setting the user interface to its reset values. When waking up,
the module must be reinitialized to ensure proper operation.
Bit 2 – PRSF Power Reduction
Support FIFO
Writing a logic
‘1’ to this bit shuts down the support FIFO by stopping the
clock to the module and setting the user interface to its reset values. When waking
up, the module must be reinitialized to ensure proper
operation.
Bit 1 – PRXA Power Reduction Rx
Buffer A
Writing a logic
‘1’ to this bit stops the clock to the stage and shuts down the
receive buffer for data path A. When waking up, the module must be reinitialized to
ensure proper operation.
Bit 0 – PRXB Power Reduction Rx
Buffer B
Writing a logic
‘1’ to this bit stops the clock to the stage and shuts down the
receive buffer for data path B. When waking up, the module must be reinitialized to
ensure proper operation.
