3.10.6.2 Port Debouncing

The ports of the ATA8510/15 feature hardware debouncing that can be used to avoid false events coming from bouncing mechanical switches. The hardware uses debounce gates for each port pin and a common debounce timer for all ports. The debouncing can be activated and deactivated independently on every port that supports this feature. The debouncing time is configurable in the range of 1 ms to 255 ms for key debouncing or 5 µs to 100 µs for LIN-bus debouncing. A level change on any port with activated debouncing resets the debounce timer.

There are two modes for debouncing. In mode 0, a port event is transmitted to the AVR only if the selected ports are stable (unchanged) for the configured debouncing time and the port values are not the same as the values before the first change (see the following section). In mode 1, a port event is transmitted to the AVR immediately. All following events are ignored for the configured debouncing time (see Debounce Fast Mode).

Debounce Stable Mode (Mode 0)

All debounce-enabled pins must be stable for the adjusted time T_debounce (typ. 10 ms). An event on any enabled pin resets the common debounce timer. After the debounce time has elapsed, the pin states are passed through to the AVR bus. An example timing diagram is shown in the following figure. In this debounce mode, short pulses are also suppressed by the debounce logic.

Figure 3-63. Example for Debounce Stable Mode Timing Diagram

The DBMD bit of the DBCR register must be cleared (DBMD = 0) for this mode. The debounce function can be enabled with the DBENx register separately for every pin. The debounce time can be set with the DBTC register and the two control bits, DBCS and DBTMS, of the DBCR register. The calculation of the debounce time is shown in Table 3-85. The debounce function of every pin must be disabled before changing any debounce setting (DBENx = 0).

Debounce Fast Mode (Mode 1)

Only the first event on every enabled pin is passed-through to the AVR core immediately. Every following event on the respective pin will be ignored until the adjustable wait time T_debounce (typ. 10 ms) has elapsed. Every event resets the common debounce timer. An example timing diagram is shown in the following figure.

Figure 3-64. Timing Diagram for Debounce Fast Mode

For this mode, bit DBMD of the DBCR register must be set (DBMD = 1). The debounce function can be enabled with the DBENx register separately for every pin. The debounce time can be set with the DBTC register and the two control bits DBCS and DBTMS of the DBCR register. The calculation of the debounce time is shown in Table 3-85. The debounce function of every pin must be disabled before changing any debounce setting (DBENx = 0).