The Debounce Timer
Compare register contains an 8-bit value that is continuously compared with the
15-bit timer value. DBTC can be set from 0 to 255. The resulting debounce timings
also depend on the DBCS and DBTMS bits of the debounce control register DBCR (see
Table 3-83 and Table 3-84). The calculation of the debounce time is shown in the following
table and the resulting timing ranges in Table 3-86. After the debouncing time a wait time caused by a handshake
synchronizer needs to be considered before the next debouncing cycle on the
appropriate pin is started (approximately 6 clock cycles of debounce clock and 6
clock cycles of I/O clock).
Table 3-85. Debounce Timing
Calculation| DBCS | DBTMS | Tdebounce_ty |
|---|
0 | 0 | (DBTC * 128 + 134) * 8 µs |
0 | 1 | (DBTC + 7) * 8 µs |
1 | 0 | (DBTC * 128 + 134) * 157 ns |
1 | 1 | (DBTC + 7) * 157 ns |
Table 3-86. Debounce Timing
Ranges| DBCS | 0
(SRC) | 1
(FRC) |
|---|
| DBTMS | 0 | 1 | 0 | 1 |
|---|
| DBTC | 0 | 255 | 0 | 255 | 0 | 255 | 0 | 255 |
|---|
| Debounce Time | 1.1 ms | 262 ms | 56 µs | 2.1 ms | 21 µs | 5.1 ms | 1.1 µs | 41.1 µs |
