45.5.2 Interrupt Enable Clear Register
| Name: | INTENCLR |
| Offset: | 0x08 |
| Reset: | 0x00000000 |
| Property: | PAC Write-Protection |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| DERREN | SERREN | ||||||||
| Access | R/W | R/W | |||||||
| Reset | 0 | 0 |
Bit 1 – DERREN Double Bit Error Interrupt Enable
Writing a ‘0’ to this bit has no effect.
Writing a '1' to this bit will clear the DERREN Interrupt Enable bit, which disabled the DERREN interrupt.
| Value | Description |
|---|---|
| 0 | The Double Bit Error Interrupt is disabled. |
| 1 | The Single Bit Error Interrupt is enabled. |
Bit 0 – SERREN Single Bit Error Interrupt Enable
Writing a ‘0’ to this bit has no effect.
Writing a '1' to this bit will clear the SERREN Interrupt Enable bit, which disabled the SERREN interrupt.
| Value | Description |
|---|---|
| 0 | The Single Bit Error Interrupt is disabled. |
| 1 | The Single Bit Error Interrupt is enabled. |