45.5.5 Fault Injection Control Register
| Name: | FLTCTRL |
| Offset: | 0x14 |
| Reset: | 0x00000000 |
| Property: | PAC Write-Protection |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| FLTMD[1:0] | |||||||||
| Access | R/W | R/W | |||||||
| Reset | 0 | 0 | |||||||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| FLTEN | |||||||||
| Access | R/W | ||||||||
| Reset | 0 |
Bits 13:12 – FLTMD[1:0] Fault Injection Mode
Note: This bitfield can only be written when FLTCTRL.FLTEN=0. Any write attempt to
this field when FLTEN=1 will fail and return a bus error.
| Value | Name | Description |
|---|---|---|
| 0x0 | DISABLE | Fault Injection Disabled. |
| 0x1 | SINGLE | Single Fault Injection on writes at address FLTADR, for the bit defined in FLTPTR.FLT1PTR. |
| 0x2 | DOUBLE | Double Fault Injection on writes at address FLTADR, for the bits defined in FLTPTR.FLT1PTR and FLTPTR.FLT2PTR. |
| 0x3 | RESERVED | Reserved. |
Bit 1 – FLTEN Fault Injection Enabled
Writing a ‘0’ to this bit disables fault injection.
Writing a ‘1’ to this bit enables fault injection at FLTADR address offset as selected by FLTMD and FLTxPTR.