45.5.6 Fault Injection Pointer Register
Note:
This register can only be written when FLTCTRL.FLTEN=0. Any write attempt to this field when FLTEN=1 will fail and return a bus error.
| Name: | FLTPTR |
| Offset: | 0x18 |
| Reset: | 0x00000000 |
| Property: | PAC Write-Protection |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| FLT2PTR[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| FLT1PTR[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 23:16 – FLT2PTR[7:0] Double fault Injection Bit Pointer
Index of the second data bit to be flipped during RAM write access at address offset FLTADR for double bit error. Valid values and corresponding bits are shown in the following table.
| FLTPTR.FLT1PTR/FLT2PTR Value | Associated Bit |
|---|---|
| 0x0 | DATA[0] |
| 0x1 | DATA[1] |
| … | … |
| 0x1F | DATA[31] |
| 0x20 | ECC[0] |
| 0x21 | ECC[1] |
| … | … |
| 0x26 | ECC[6] |
| 0x27 - 0xFF | Reserved |
Bits 7:0 – FLT1PTR[7:0] Single Fault Injection Bit Pointer
Index of the data bit to be flipped during RAM write access at MCRAMC address offset FLTADR for single bit error. Valid values and corresponding bits are shown in the following table.
| FLTPTR.FLT1PTR/FLT2PTR Value | Associated Bit |
|---|---|
| 0x0 | DATA[0] |
| 0x1 | DATA[1] |
| … | … |
| 0x1F | DATA[31] |
| 0x20 | ECC[0] |
| 0x21 | ECC[1] |
| … | … |
| 0x26 | ECC[6] |
| 0x27 - 0xFF | Reserved |