45.5.7 Fault Injection Address Register
Note:
This register can only be written when FLTCTRL.FLTEN = 0. Any write attempt to this field when FLTEN = 1 will fail and return a bus error.
Name: | FLTADR |
Offset: | 0x1C |
Reset: | 0x00000000 |
Property: | PAC Write-Protection |
Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
Access | |||||||||
Reset |
Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
FLTADR[23:16] | |||||||||
Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
FLTADR[15:8] | |||||||||
Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
FLTADR[7:0] | |||||||||
Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bits 23:0 – FLTADR[23:0] Fault Address Offset
MCRAMC relative address of the word where the fault injection will occur when written at. Valid values range respectively from 0 to 0xFFFC, 0x7FFC and 0x3FFC for a 64 Kb, 32 Kb and 16 Kb SRAM.
The MCRAMC system bus base address should be added to this relative value to know the corresponding system bus address to be corrupted.