45.5.10 Error Capture Syndrome Register
| Name: | ERRCSYN |
| Offset: | 0x28 |
| Reset: | 0x00000000 |
| Property: | - |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| ERR2 | ERR1 | ||||||||
| Access | R | R | |||||||
| Reset | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| ERCSYN[6:0] | |||||||||
| Access | R | R | R | R | R | R | R | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||
Bit 15 – ERR2 ECC Double Bit Error
| Value | Description |
|---|---|
| 0 | Not a Double bit error. |
| 1 | Double bit error. |
Bit 14 – ERR1 ECC Single Bit Error
| Value | Description |
|---|---|
| 0 | Not a Single bit error. |
| 1 | Single bit error. |
Bits 6:0 – ERCSYN[6:0] ECC SECDED Error Capture Syndrome
ECC SECDED Syndrome bits read at the ERCADR address offset from the MCRAMC system bus base address.