35.17 ADC

Table 35-23. Power Supply, Reference and Input Range
Operating conditions:
  • VDD = 3.0V
  • TA = 25°C
  • Applies to all allowed combinations of VREF selections and sample rates, unless otherwise specified
SymbolDescriptionMin.Typ.✝Max.UnitConditions
VDDSupply voltage1.62—5.5V
VREFReference voltage0.512—VDDV
CINInput capacitance—3—pF
RINInput resistance—3—kΩ
VINInput voltage range0—VREFV

✝ Data in the “Typ.” column is measured at TA = 25°C and VDD = 3.0V unless otherwise specified. These parameters are not tested and are for design guidance only.

Table 35-24. Clock and Timing Characteristics
Operating conditions:
  • Applies to all allowed combinations of VREF selections and sample rates, unless otherwise specified
SymbolDescriptionMin.Typ.✝Max.UnitConditions
CLK_ADCADC clock frequency300—2000kHzREFSEL = Internal Reference
300—2000kHz

REFSEL = External Reference

REFSEL = VDD

✝ Data in the “Typ.” column is measured at TA = 25°C and VDD = 3.0V unless otherwise specified. These parameters are not tested and are for design guidance only.

Table 35-25. Accuracy Characteristics (1)
Operating conditions:
  • VDD = 3.0V
  • VREF = External 3.0V
  • TA = 25°C
  • fCLK_ADC = 1 MHz
  • CPU in Sleep mode
SymbolDescriptionMin.Typ.✝Max.UnitConditions
ResResolution——10bit
EINLIntegral nonlinearity error—0.3—LSb
EDNLDifferential nonlinearity error—0.3—LSb
EOFFOffset error—0.3—LSb
EGAINGain error—2—LSb
ETTotal unadjusted error—3.5—LSb

✝ Data in the “Typ.” column is measured at TA = 25°C and VDD = 3.0V unless otherwise specified. These parameters are not tested and are for design guidance only.

Note:
  1. These values are based on characterization and are not covered by production test limits.