35.15 TWI

Figure 35-8. TWI - Timing Requirements

Table 35-20. TWI - Timing Specifications
Symbol	Description	Min.	Typ.✝	Max.	Unit	Condition
f_SCL	SCL clock frequency ⁽¹⁾	—	—	1000	kHz	Fast-mode Plus (F_m+)
		—	—	400	kHz	Fast-mode (F_m)
		—	—	100	kHz	Standard-mode (S_m)
V_IL	Low level input voltage	-0.5	—	0.3×V_DD	V	INPUTLVL = `0x0` (I²C)
V_IL	Low level input voltage	-0.5	—	0.8	V	INPUTLVL = `0x1` (SMBUS) V_DD > 2.5V
V_IH	High level input voltage ⁽³⁾	0.7×V_DD	—	V_DD+0.5V	V	INPUTLVL = `0x0` (I²C)
		1.35	—	V_DD+0.5V		INPUTLVL = `0x1` (SMBUS) 0°C ≤ T_A ≤ +125°C
		1.5	—	V_DD+0.5V		INPUTLVL = `0x1` (SMBUS) -40°C ≤ T_A ≤ +125°C
V_HYS	Hysteresis of Schmitt Trigger inputs	0.05×V_DD	—	—	V	INPUTLVL = `0x0` (I²C)
V_HYS	Hysteresis of Schmitt Trigger inputs	—	0.1	—	V	INPUTLVL = `0x1` (SMBUS)
V_OL	Output low voltage ⁽²⁾	—	—	0.6	V	I_load = 6 mA, V_DD > 2.5V
		—	—	0.4		I_load = 3 mA, V_DD > 2V
		—	—	0.2×V_DD		I_load = 2 mA, V_DD ≤ 2V
t_SP ^*	Spike pulse width suppressed by the input filter	0	—	t_SPM	ns
t_SPM ^*	Input filter delay	50	—	200	ns
t_{HD_DAT} ^*	Data hold time	—	0	—	ns	SDAHOLD[1:0] = `0x0`
		—	50	—		SDAHOLD[1:0] = `0x1`
		—	300	—		SDAHOLD[1:0] = `0x2`
		300	500	900		SDAHOLD[1:0] = `0x3`
✝ Data in the “Typ.” column is measured at T_A = 25°C and V_DD = 3.0V unless otherwise specified. These parameters are not tested and are for design guidance only. * These parameters are not tested and are for design guidance only. Note: System clock frequency needs to be at least ten times faster than the TWI bus clock (f_{CLK_PER} ≥ 10x f_SCL) but additional limitations may apply depending on baud rate. Refer to the TWI chapter for more detailed information. Fast-mode Plus full 20 mA drive capability is not supported. If TWI pins are above V_DD+0.5V, the current will flow from the TWI pin(s) to V_DD.