22.6.5 CCP9 Control 3 Low Register(1)
Note:
- This register is implemented in the MCCP9 module only.
| Name: | CCP9CON3L |
| Offset: | 0xA78 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| DT[5:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | |||
Bits 5:0 – DT[5:0] CCP9 Dead-Time Select bits
| Value | Description |
|---|---|
111111 |
Inserts 63 dead-time delay periods between complementary output signals |
111110 |
Inserts 62 dead-time delay periods between complementary output signals |
| ... | |
000010 |
Inserts 2 dead-time delay periods between complementary output signals |
000001 |
Inserts 1 dead-time delay periods between complementary output signals |
000000 |
Dead-time logic is disabled |