43.14 XOSC32 AC Electrical Specifications

Table 43-18. XOSC32 AC Electrical Specifications
AC Characteristics			Standard Operating Conditions: V_DD = 1.9V to 3.6V (unless otherwise stated) Operating Temperature: -40°C ≤ T_A ≤ +85°C for Industrial Temp -40°C ≤ T_A ≤ +125°C for Extended Temp
Param. No.	Symbol	Characteristics	Min.	Typ.	Max.	Units	Conditions⁽¹⁾
XOSC32_1	F_OSC_XOSC32	XOSC32 oscillator crystal frequency	—	32.764	—	kHz	XIN32, XOUT32 secondary oscillator
XOSC32_3	C_XIN32	XOSC32 XIN32 parasitic pin capacitance	—	0.4	—	pF	0.4 pF at the SOC pins and 2.4 pF on the WBZ35x Module
XOSC32_3	C_XIN32	XOSC32 XIN32 parasitic pin capacitance	—	2.4	—	pF	0.4 pF at the SOC pins and 2.4 pF on the WBZ35x Module
XOSC32_5	C_XOUT32	XOSC32 XOUT32 parasitic pin capacitance	—	0.4	—	pF	0.4 pF at the SOC pins and 2.4 pF on the WBZ35x Module
XOSC32_5	C_XOUT32	XOSC32 XOUT32 parasitic pin capacitance	—	2.4	—	pF	0.4 pF at the SOC pins and 2.4 pF on the WBZ35x Module
XOSC32_11	C_LOAD_X32⁽⁴⁾	32.768 kHz crystal load capacitance	—	11	—	pF	—
XOSC32_13	ESR_X32	32.768 kHz crystal ESR	—	75	100	kΩ	—
XOSC32_15	TOSC32	TOSC32 = 1/FOSC_XOSC32	—	30.5	—	µs	See parameter XOSC32_1 for FOSC_XOSC32 value
XOSC32_17	XOSC32_ST⁽³⁾	XOSC32 crystal start-up time	—	1024	—	TOSC	Crystal stabilization time only not oscillator ready
Note: V_DDIO = AV_DD = 3.3V. The parameters are characterized but not tested in manufacturing. This is for guidance only. A major component of crystal start-up time is based on the second party crystal MFG parasitic that is outside the scope of this specification. If this is a major concern, the customer might need to characterize this based on their design choices. The test conditions for the crystal load capacitor calculation are as follows: Standard PCB trace capacitance = 1.5 pF per 12.5 mm (0.5 inches) (in other words, PCB STD TRACE W = 0.175 mm, H = 36 μm, T = 113 μm) Xtal PCB capacitance typical; therefore, ~= 2.5 pF for a tight PCB xtal layout For CXIN and CXOUT within 4 pF of each other, assume CXTAL_EFF = ((CXIN / 2) Note: Averaging CXIN and CXOUT will affect the final calculated CLOAD value by less than the tolerance of the capacitor selection. Equation 1: $M F G C L O A D S p e c = {([C X I N + C 1] * [C X O U T + C 2]) / [C X I N + C 1 + C 2 + C X O U T]} + e s t i m a t e d o s c i l l a t o r P C B s t r a y c a p a c i t a n c e$ Assuming C1 = C2 and CXin ~= CXout, the formula can be further simplified and restated to solve for C1 and C2 by: Equation 43-3. Equation 2 (In other words: Simplified Equation 1) $C 1 = C 2 = ((2 * M F G C L O A D S p e c) - C X T A L_E F F - (2 * P C B c a p a c i t a n c e))$ Example: XTAL Mfg CLOAD Data Sheet Spec = 12 pF PCB XTAL trace Capacitance = 2.5 pF CXIN pin = 6.5 pF, CXOUT pin = 4.5 pF therefore CXTAL_EFF = ((CXIN / 2) CXTAL_EFF = ((6.5 + 4.5)/2) = 5.5 pF C1 = C2 = ((2 * MFG Cload spec) – CXTAL_EFF – (2 * PCB capacitance)) C1 = C2 = (24 – 5.5 – (2 * 2.5)) C1 = C2 = (24 – 5.5 – 5) C1 = C2 = 13.5 pF (Always rounded down) C1 = C2 = 13 pF (in other words, for hypothetical example crystal external load capacitors) User C1 = C2 = 13 pF ≤ CLOAD_X32 (max.) spec User selectable in OSC32KCTRL.STARTUP.