43.16 DAC Module Electrical Specifications

Table 43-20. DAC Module Electrical Specifications
DC Characteristics⁽⁷⁾					Standard Operating Conditions: V_DD = 1.9V to 3.6V (unless otherwise stated) Operating Temperature: -40°C ≤ T_A ≤ +85°C for Industrial Temp -40°C ≤ T_A ≤ +125°C for Extended Temp
Param. No.	Symbol	Characteristics			Min.	Typ.	Max.	Units	Conditions
DAC_1	D_RES	DAC resolution			—	—	7	Bits	—
DAC_3	D_CLK	Internal DAC clock frequency (GCLK_DAC)			—	—	—	MHz	V_DDANA(min)
DAC_5	D_SAMP	DAC sampling rate	Low power		—	—	—	Msps	±4 LSB of final value for step size ≤ 100 LSB at C_LOAD and R_LOAD w/V_DDANA = 3.3V
DAC_5	D_SAMP	DAC sampling rate	High power		—	—	1	Msps
DAC_7	V_OUT	Output voltage range			GNDANA+___	—	VDDANA-___	V	External pin (Buffered) V_REF = V_DDANA at C_LOAD and R_LOAD
					GNDANA+___	—	VREF-___	V	External pin (Buffered) at C_LOAD and R_LOAD (V_REF < (V_DDANA-150 mv))
					GNDANA	—	VREF-___	V	Internal (No buffer)
DAC_9	V_REF^(1,2,3)	DAC reference input option	REFSEL = External		V_DDANA(min) or ≥ 2.4V whichever is greater	—	V_DDANA	V	External reference CTRLB.REFSEL[1:0] = 0x2, V_REFAB ≤ V_DDANA and V_REF bypass Cap = 0.01 µf
			REFSEL = External		V_DDANA(min) or ≥ 2.4V whichever is greater	—	V_DDANA	V	External reference CTRLB.REFSEL[1:0] = 0x0, V_REFAU ≤ V_DDANA and V_REF bypass Cap = 0.01 µf
			REFSEL = Internal		V_DDANA(min) or ≥ 2.4V whichever is greater	—	V_DDANA		V_DDANA ≥ 2.4V
DAC_11	C_LOAD	DAC Out max load to meet VOUT and TSET			—	—	40	pf	For buffered output
DAC_13	R_LOAD	DAC Out max load to meet VOUT and TSET			33	—	—	KΩ	Minimum of 33K Ω resistance needed for buffered output path
DAC_15	Tset	DAC settling time			—	4	—	µs	±4 LSB of final value for step size ≤ 100 LSB at C_LOAD and R_LOAD w/ V_DDANA = 3.3V
DAC_17	Tset_FS	DAC full scale settling time			—	10	—	µs	±4 LSB of final value for step size from 10% to 90% at C_LOAD and R_LOAD w/ V_DDANA = 3.3V
Single Ended Mode^(1,2,3,5)
SDAC_19	INL⁽⁶⁾	Integral non linearity			-3	0	2	LSB	V_REF Internal = V_DDANA = 3.3V w/ C_LOAD and R_LOAD
SDAC_21	DNL⁽⁶⁾	Differential non linearity			-2	1	2	LSB
SDAC_23	GERR⁽⁶⁾	Gain error		REFSEL = V_DDANA	-1.56	—	-0.119	LSB
SDAC_25	EOFF⁽⁶⁾	Offset error		REFSEL = V_DDANA	-1.111	—	0.485	LSB	V_REF Internal = V_DDANA = 3.3V w/ C_LOAD and R_LOAD
Note: DAC internal bandgap reference voltage 2.4V ≤ REFSEL ≤ V_DDANA. DAC reference voltages < 2.4V are not practical, and peripheral performance is not ensured. DAC functional device operation with either internal or external V_REF < 2.4V is ensured but not characterized. DAC_ will function but with degraded performance. DAC accuracy is limited by user's application noise/accuracy on V_DDANA, GNDANA and V_REF accuracy/drift. Value taken over 7 harmonics. 12-bit mode Over V_OUT range defined by the DAC_7 parameter These parameters are characterized but not tested in manufacturing.