18.7.16 PLL1 Feed-Back Divider

Table 18-21. Register Bit Attribute Legend
SymbolDescriptionSymbolDescriptionSymbolDescription
RReadable bitHCCleared by Hardware(Grey cell)Unimplemented
WWritable bitHSSet by HardwareXBit is unknown at Reset
KWrite to clearSSoftware settable bit
Name: PLL1FBDIV
Offset: 0x58
Reset: 0x00000000
Property: PAC Write-Protection

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
       FBDIV[9:8] 
Access R/WR/W 
Reset 00 
Bit 76543210 
 FBDIV[7:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 

Bits 9:0 – FBDIV[9:0] PLL1 Feed-Back Divider Factor

This field determines the ratio of the PLL's VCO output frequency to the PLL Reference input frequency. Writing to the FBDIV bits will cause lock to be lost.

The value of FBDIV, (i.e. PLLFBDIV) must be within the range 21 ≤ FBDIV ≤ 1023.

Note: Note: The frequency of the Voltage Controlled Oscillator (VCO) giving the PLL0 oscillation is given by the formula:

FVCO = FCKR * (FBDIV / REFDIV), (i.e., Must be between 800 MHz and 1600 MHz).

fCKR , REFDIV and FBDIV must be selected to satisfy this condition.