18.7.7 External Multipurpose Crystal Oscillator Control B
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | XOSCCTRLB |
| Offset: | 0x18 |
| Reset: | 0x00000000 |
| Property: | PAC Write-Protection |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| WRTLOCK | |||||||||
| Access | R/W | ||||||||
| Reset | 0 |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| GBW[1:0] | GRES | GMAN[1:0] | |||||||
| Access | R/W | R/W | R/W | R/W | R/W | ||||
| Reset | 0 | 0 | 0 | 0 | 0 | ||||
Bit 31 – WRTLOCK Write Lock for CTRLB register
Note: Once the WRTLOCK bit is set, it can only be cleared by a reset.
| Value | Description |
|---|---|
| 0 | The XOSCCTRLB register can be modified by a system write. |
| 1 | The XOSCCTRLB register is write protected. |
Bits 4:3 – GBW[1:0] AGC Gain Bandwidth (Gain Step Loop Delay)
Note:
- These bits are ignored if XOSCCTRLA.AGC=0, only used if XOSCCTRLA.AGC=1.
- The default setting should meet the vast majority of user crystal requirements. Internally, there are a maximum of 16 and a minimum of one AGC linear gain search steps the logic may utilize before locking. A lock will occur when the crystal is oscillating and the amplitude of the crystal signal is between a max and min fixed internal threshold for a fixed number of valid oscillator cycles. The GBW is the time for each of the possible AGC search steps settling time to allow the crystal to startup and amplitude to stabilize before determining if a lock is true or to continue to search for the required gain. The GBW bits represent a balance between start-up time and crystal power optimization. The lower the GBW delay time the faster the crystal start-up time but potentially at a higher crystal power level. The higher the GBW delay time the slower the crystal start-up time but with a better crystal power optimization level (i.e., less power).
- Use of resonators with this product have not been confirmed - use at your own discretion. When using a resonator, due to their long start-up times, it may be necessary to use a longer AGC GBW step settling time.
| Value | Description |
|---|---|
| 11 | Reserved |
| 10 | Reserved |
| 01 | Update loop every ~25ms |
| 00 | Update loop every ~6.25ms (Default) |
Bit 2 – GRES Internal XOSC Gain Resistor
Important: If XOSCCTRLA.XTALEN = 0, clock oscillator instead of a
crystal, then this bit is ignored. In all other configurations XOSCCTRLA.AGC=”x”
or GMAN =0bxx this bit SHOULD always be set, XOSCCTRLB. GRES=1, by the
user except in the case where the user is utilizing an external gain
resistor between the XOSC XIN and XOUT pins.
| Value | Description |
|---|---|
| 0 | Disconnect internal XOSC shunt Gain resistor (Default) |
| 1 | Use internal XOSC shunt Gain resistor |
Bits 1:0 – GMAN[1:0] Manual User Crystal Control Gain Setting (XOSCCTRLA.AGC=0)
Gm3 >Gm3 >Gm1>Gm0
Note: These bits are ignored if XOSCCTRLA.AGC=1.
| Value | Description |
|---|---|
| 11 | Gain_3 |
| 10 | Gain_2 |
| 01 | Gain_1 |
| 00 | Gain_0 (Default) |