18.7.5 Status
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | STATUS |
| Offset: | 0x10 |
| Reset: | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| PLL1LOCK | PLL0LOCK | ||||||||
| Access | R | R | |||||||
| Reset | 0 | 0 |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| DFLLFAIL | DFLLRCS | DFLLUNF | DFLLOVF | DFLLLOCK | DFLLRDY | ||||
| Access | R | R | R | R | R | R | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| XOSCCKSW | CLKFAIL | XOSCFAIL | XOSCRDY | ||||||
| Access | R | R | R | R/W | |||||
| Reset | 0 | 0 | 0 | 0 |
Bits 24, 25 – PLLnLOCK PLL Lock
| Value | Description |
|---|---|
| 0 | PLL Lock edge is not detected. |
| 1 | PLL Lock edge is detected. |
Bit 13 – DFLLFAIL DFLL Startup Failure
| Value | Description |
|---|---|
| 0 | DFLL Startup failure is not detected. |
| 1 | DFLL Startup failure is detected. |
Bit 12 – DFLLRCS DFLL Reference Clock Stopped
| Value | Description |
|---|---|
| 0 | DFLL reference clock is running. |
| 1 | DFLL reference clock has stopped. |
Bit 11 – DFLLUNF DFLL Tuner Underflow
| Value | Description |
|---|---|
| 0 | DFLL Tuner Underflow is not detected. |
| 1 | DFLL Tuner Underflow is detected. |
Bit 10 – DFLLOVF DFLL Tuner Overflow
| Value | Description |
|---|---|
| 0 | DFLL Tuner Overflow is not detected. |
| 1 | DFLL Tuner Overflow is detected. |
Bit 9 – DFLLLOCK DFLL Lock
| Value | Description |
|---|---|
| 0 | DFLL lock is not detected. |
| 1 | DFLL lock is detected. |
Bit 8 – DFLLRDY DFLL Ready
| Value | Description |
|---|---|
| 0 | DFLL is not ready. |
| 1 | DFLL is stable and ready to be used as a clock source. |
Bit 3 – XOSCCKSW XOSC Clock Switch
| Value | Description |
|---|---|
| 0 | XOSC is not switched and provides the external clock or crystal oscillator clock. |
| 1 | XOSC is switched and provides the safe clock. |
Bit 2 – CLKFAIL XOSC Clock Failure
| Value | Description |
|---|---|
| 0 | XOSC Clock failure is not detected. |
| 1 | XOSC Clock failure is detected. |
Bit 1 – XOSCFAIL XOSC Startup Failure
| Value | Description |
|---|---|
| 0 | XOSC Startup failure is not detected. |
| 1 | XOSC Startup failure is detected. |
Bit 0 – XOSCRDY XOSC Ready
Note: If the CFD is enabled and the XOSC clock is failing, the XOSCRDY status bit
remains high, if already set.
| Value | Description |
|---|---|
| 0 | XOSC is not ready. |
| 1 | XOSC is stable and ready to be used as a clock source. |