18.7.17 PLL0 Reference Divider

Table 18-22. Register Bit Attribute Legend
SymbolDescriptionSymbolDescriptionSymbolDescription
RReadable bitHCCleared by Hardware(Grey cell)Unimplemented
WWritable bitHSSet by HardwareXBit is unknown at Reset
KWrite to clearSSoftware settable bit
Name: PLL0REFDIV
Offset: 0x48
Reset: 0x00000000
Property: PAC Write-Protection, Enable-Protected

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
          
Access  
Reset  
Bit 76543210 
   REFDIV[5:0] 
Access R/WR/WR/WR/WR/WR/W 
Reset 000000 

Bits 5:0 – REFDIV[5:0] PLL0 Reference Division Factor

This field determines the division factor of the PLL0 input reference frequency. Writing to the REFDIV bits will cause lock to be lost. REFDIV value must be in the range of 1 ≤ REFDIV ≤ 63.

The frequency after the reference divider (FPFD) is given by the formula:

FPFD = FCKR / REFDIV (i.e., FPFD must always be between 4 MHz to 48 MHz.