18.7.21 Fractional Divider 0
Note:
- FCLK_PLLFRC0 = (FCLK_PLL1 / (2 x (INTDIV + (REMDIV / 512)))).
- The maximum permitted fractional output frequency, FCLK_PLLFRC0, must always be limited to 300MHz by the user.
- Setting both INTDIV and REMDIV = 0 will yield FCLK_PLLFRC0 = FCLK_PLL1 which effectively bypasses the fractional divider module in which case the user must limit the output of PLL1 to the fractional divider module to FPLL1 = FCLK_PLL1 = 300MHz max.
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | FRACDIV0 |
| Offset: | 0x6C |
| Reset: | 0x00200000 |
| Property: | PAC Write-Protection, Write-Synchronized |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| INTDIV[14:8] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 1 | 0 | ||
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| INTDIV[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| REMDIV[8:1] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| REMDIV[0] | |||||||||
| Access | R/W | ||||||||
| Reset | 0 |
Bits 30:16 – INTDIV[14:0] Frequency Division Factor Integer Part
This field determines the integer part of the frequency divider and must be between 0 ≤ INTDIV ≤ 32767.
INTDIV (Default) = 0x20 = 32 decimal.
Bits 15:7 – REMDIV[8:0] Frequency Division Factor Remainder Part
This field determines the reminder part of the frequency divider and must be between 0 ≤ REMDIV ≤ 511.