18.7.21 Fractional Divider 0

Note:
  1. FCLK_PLLFRC0 = (FCLK_PLL1 / (2 x (INTDIV + (REMDIV / 512)))).
  2. The maximum permitted fractional output frequency, FCLK_PLLFRC0, must always be limited to 300MHz by the user.
  3. Setting both INTDIV and REMDIV = 0 will yield FCLK_PLLFRC0 = FCLK_PLL1 which effectively bypasses the fractional divider module in which case the user must limit the output of PLL1 to the fractional divider module to FPLL1 = FCLK_PLL1 = 300MHz max.
Table 18-26. Register Bit Attribute Legend
SymbolDescriptionSymbolDescriptionSymbolDescription
RReadable bitHCCleared by Hardware(Grey cell)Unimplemented
WWritable bitHSSet by HardwareXBit is unknown at Reset
KWrite to clearSSoftware settable bit
Name: FRACDIV0
Offset: 0x6C
Reset: 0x00200000
Property: PAC Write-Protection, Write-Synchronized

Bit 3130292827262524 
  INTDIV[14:8] 
Access R/WR/WR/WR/WR/WR/WR/W 
Reset 0000010 
Bit 2322212019181716 
 INTDIV[7:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 15141312111098 
 REMDIV[8:1] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 76543210 
 REMDIV[0]        
Access R/W 
Reset 0 

Bits 30:16 – INTDIV[14:0] Frequency Division Factor Integer Part

This field determines the integer part of the frequency divider and must be between 0 ≤ INTDIV ≤ 32767.

INTDIV (Default) = 0x20 = 32 decimal.

Bits 15:7 – REMDIV[8:0] Frequency Division Factor Remainder Part

This field determines the reminder part of the frequency divider and must be between 0 ≤ REMDIV ≤ 511.