18.7.1 Event Control
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | EVCTRL |
| Offset: | 0x00 |
| Reset: | 0x00000000 |
| Property: | PAC Write-Protection |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CFDEO | |||||||||
| Access | R/W | ||||||||
| Reset | 0 |
Bit 0 – CFDEO Clock Failure Detector Event Output Enable
This bit indicates whether the XOSC Clock Failure detector event output is enabled and an output event will be generated when the XOSC Clock Failure detector detects a clock failure.
Note: To prevent false event generation, the bit CFDEO must be set or cleared only
when the XOSC is disabled (XOSCCTRLn.ENABLE=0).
| Value | Description |
|---|---|
| 0 | Clock Failure detector event output is disabled and an event will not be generated on a clock fail. |
| 1 | Clock Failure detector event output is enabled and an event will be generated on a clock fail. |