18.7.12 DFLL48M Multiplier

Table 18-15. Register Bit Attribute Legend
SymbolDescriptionSymbolDescriptionSymbolDescription
RReadable bitHCCleared by Hardware(Grey cell)Unimplemented
WWritable bitHSSet by HardwareXBit is unknown at Reset
KWrite to clearSSoftware settable bit
Name: DFLLMUL
Offset: 0x3C
Reset: 0x00000000
Property: PAC Write-Protection, Write-Synchronized

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
  STEP[6:0] 
Access R/WR/WR/WR/WR/WR/WR/W 
Reset 0000000 
Bit 15141312111098 
 MUL[15:8] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 76543210 
 MUL[7:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 

Bits 22:16 – STEP[6:0] Tune Maximum Step

This bit group indicates the maximum step size allowed during tune adjustment in closed-loop mode. When adjusting to a new frequency, the expected output frequency overshoot depends on this step size.

Note: STEP[6:0] is nothing more than the first tuner adjustment value from where the tune search will start. Depending if the current DFLL frequency is slower of faster than the targeted frequency, the next tune register value is tune+step or tune-step. Each time the current frequency changes from slower to faster or faster to slower, step is divided by 2 until the minimum value of 1.

Example 1:

If STEP[6:0] = 64, dichotomic search will be:

  • step1 = +/-64
  • step2 = +/-32
  • step3 = +/-16
  • step4 = +/-8
  • step5 = +/-4
  • step6 = +/-2
  • step7 = +/-1

Example 2:

If STEP[6:0] = 15, dichotomic search will be:

  • step1 = +/-15
  • step2 = +/-7
  • step3 = +/-3
  • step4 = +/-1

Bits 15:0 – MUL[15:0] DFLL Multiply Factor

This field determines the ratio of the CLK_DFLL output frequency to the CLK_DFLL_REF input frequency. Writing to the MUL bits will cause the lock to be lost and the DFLLTUNE.TUNE register value to be reset to its midpoint, 0b000_0000.

Example: CLK_DFLL_REF = XTAL, 32.768 kHz, 100 ppm, DFLLMUL.MUL[15:0] = 1464 = 0x5B8, then DFLL48 = 47.97 MHz.