18.7.15 PLL0 Feed-Back Divider
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | PLL0FBDIV |
| Offset: | 0x44 |
| Reset: | 0x00000000 |
| Property: | PAC Write-Protection |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| FBDIV[9:8] | |||||||||
| Access | R/W | R/W | |||||||
| Reset | 0 | 0 | |||||||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| FBDIV[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 9:0 – FBDIV[9:0] PLL0 Feed-Back Divider Factor
This field determines the ratio of the PLL's VCO output frequency to the PLL Reference input frequency. Writing to the FBDIV bits will cause lock to be lost.
The value of FBDIV, (i.e. PLLFBDIV) must be within the range 21 ≤ FBDIV ≤ 1023.
Note: Note: The frequency of the
Voltage Controlled Oscillator (VCO) giving the PLL0 oscillation is given by the
formula:
FVCO = FCKR * (FBDIV / REFDIV), (i.e., Must be between 800 MHz and 1600 MHz).
fCKR , REFDIV and FBDIV must be selected to satisfy this condition.