30.10.6 MediaLB Interrupt Enable Register

Table 30-30. Register Bit Attribute Legend
SymbolDescriptionSymbolDescriptionSymbolDescription
RReadable bitHCCleared by Hardware(Grey cell)Unimplemented
WWritable bitHSSet by HardwareXBit is unknown at Reset
KWrite to clearSSoftware settable bit——
Name: MIEN
Offset: 0x42C
Reset: 0x00000000
Property: Read/Write

Bit 3130292827262524 
   CTX_BREAKCTX_PECTX_DONECRX_BREAKCRX_PECRX_DONE 
Access R/WR/WR/WR/WR/WR/W 
Reset 000000 
Bit 2322212019181716 
  ATX_BREAKATX_PEATX_DONEARX_BREAKARX_PEARX_DONESYNC_PE 
Access R/WR/WR/WR/WR/WR/WR/W 
Reset 0000000 
Bit 15141312111098 
          
Access  
Reset  
Bit 76543210 
       ISOC_BUFOISOC_PE 
Access R/WR/W 
Reset 00 

Bit 29 – CTX_BREAK Control Tx Break Enable

ValueDescription
1A ReceiverBreak response received from the receiver on a control Tx channel causes the appropriate channel bit in the MS0 or MS1 registers to be set.

Bit 28 – CTX_PE Control Tx Protocol Error Enable

ValueDescription
1A ProtocolError generated by the receiver on a control Tx channel causes the appropriate channel bit in the MS0 or MS1 registers to be set.

Bit 27 – CTX_DONE Control Tx Packet Done Enable

ValueDescription
1A packet transmitted with no errors on a control Tx channel causes the appropriate channel bit in the MS0 or MS1 registers to be set.

Bit 26 – CRX_BREAK Control Rx Break Enable

Rx channel causes the appropriate channel bit in the MS0 or MS1 registers to be set.

ValueDescription
1A ControlBreak command received from the transmitter on a control.

Bit 25 – CRX_PE Control Rx Protocol Error Enable

ValueDescription
1A ProtocolError detected on a control Rx channel causes the appropriate channel bit in the MS0 or MS1 registers to be set.

Bit 24 – CRX_DONE Control Rx Packet Done Enable

ValueDescription
1A packet received with no errors on a control Rx channel causes the appropriate channel bit in the MS0 or MS1 registers to be set.

Bit 22 – ATX_BREAK Asynchronous Tx Break Enable

ValueDescription
1A ReceiverBreak response received from the receiver on an asynchronous Tx channel causes the appropriate channel bit in the MS0 or MS1 registers to be set.

Bit 21 – ATX_PE Asynchronous Tx Protocol Error Enable

ValueDescription
1A ProtocolError generated by the receiver on an asynchronous Tx channel causes the appropriate channel bit in the MS0 or MS1 registers to be set.

Bit 20 – ATX_DONE Asynchronous Tx Packet Done Enable

Tx channel causes the appropriate channel bit in the MS0 or MS1 registers to be set.

ValueDescription
1A packet transmitted with no errors on an asynchronous

Bit 19 – ARX_BREAK Asynchronous Rx Break Enable

ValueDescription
1A AsyncBreak command received from the transmitter on an asynchronous Rx channel causes the appropriate channel bit in the MS0 or MS1 registers to be set.

Bit 18 – ARX_PE Asynchronous Rx Protocol Error Enable

ValueDescription
1A ProtocolError detected on an asynchronous Rx channel causes the appropriate channel bit in the MS0 or MS1 registers to be set.

Bit 17 – ARX_DONE Asynchronous Rx Done Enable

ValueDescription
1A packet received with no errors on an asynchronous Rx channel causes the appropriate channel bit in the MS0 or MS1 registers to be set.

Bit 16 – SYNC_PE Synchronous Protocol Error Enable

ValueDescription
1A ProtocolError detected on a synchronous Rx channel causes the appropriate channel bit in the MS0 or MS1 registers to be set.

Bit 1 – ISOC_BUFO Isochronous Rx Buffer Overflow Enable

ValueDescription
1A buffer overflow on an isochronous Rx channel causes the appropriate channel bit in the MS0 or MS1 registers to be set. This occurs only when isochronous flow control is disabled.

Bit 0 – ISOC_PE Isochronous Rx Protocol Error Enable

ValueDescription
1A ProtocolError detected on an isochronous Rx channel causes the appropriate channel bit in the MS0 or MS1 registers to be set.