The HC can control and monitor general operation of the HBI
block by reading and writing the HBI Control Register (HCTL) through the I/O
interface. Each bit of HCTL is read/write.
Table 30-32. Register Bit Attribute
Legend
Symbol
Description
Symbol
Description
Symbol
Description
R
Readable bit
HC
Cleared by Hardware
(Grey cell)
Unimplemented
W
Writable bit
HS
Set by Hardware
X
Bit is unknown at Reset
K
Write to clear
S
Software settable bit
—
—
Name:
HCTL
Offset:
0x480
Reset:
0x00000000
Property:
Read/Write
Bit
31
30
29
28
27
26
25
24
Access
Reset
Bit
23
22
21
20
19
18
17
16
Access
Reset
Bit
15
14
13
12
11
10
9
8
EN
Access
R/W
Reset
0
Bit
7
6
5
4
3
2
1
0
RST1
RST0
Access
R/W
R/W
Reset
0
0
Bit 15 – EN HBI Enable
Value
Description
0
Disabled
1
Enabled
Bit 1 – RST1 Address Generation Unit 1 Software
Reset
Value
Description
0
Active
1
Reset
Bit 0 – RST0 Address Generation Unit 0 Software
Reset
Value
Description
0
Active
1
Reset
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