30.10.12 HBI Channel Error 1 Register
HCERn status bits are set when hardware detects hardware errors on the given logical channel, including:
- Channel opened, but not enabled,
- Channel opened, but not enabled,
- Out-of-range PML for asynchronous or control Tx channels
Symbol | Description | Symbol | Description | Symbol | Description |
---|---|---|---|---|---|
R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
K | Write to clear | S | Software settable bit | — | — |
Name: | HCER1 |
Offset: | 0x494 |
Reset: | 0x00000000 |
Property: | Read-only |
Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
CERR[63:56] | |||||||||
Access | R/W/HS | R/W/HS | R/W/HS | R/W/HS | R/W/HS | R/W/HS | R/W/HS | R/W/HS | |
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
CERR[55:48] | |||||||||
Access | R/W/HS | R/W/HS | R/W/HS | R/W/HS | R/W/HS | R/W/HS | R/W/HS | R/W/HS | |
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
CERR[47:40] | |||||||||
Access | R/W/HS | R/W/HS | R/W/HS | R/W/HS | R/W/HS | R/W/HS | R/W/HS | R/W/HS | |
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
CERR[39:32] | |||||||||
Access | R/W/HS | R/W/HS | R/W/HS | R/W/HS | R/W/HS | R/W/HS | R/W/HS | R/W/HS | |
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bits 31:0 – CERR[63:32] Bitwise Channel Error Bit [63:32]
CERR[n] = 1 indicates that a fatal error occurred on channel n.