30.10.25 AHB Control Register
The AHB Control (ACTL) register is written by the Host Controller (HC) to configure the AHB block for channel interrupts. ACTL contains three configuration fields, one is used to select the DMA mode, one is used to multiplex channel interrupts onto a single interrupt signal, and the last selects the method of clearing channel interrupts (either software or hardware).
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | ACTL |
| Offset: | 0x7C0 |
| Reset: | 0x00000000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| MPB | DMAMODE | SMX | SCE | ||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 |
Bit 4 – MPB DMA Packet Buffering Mode
| Value | Description |
|---|---|
| 0 | Single-packet mode |
| 1 | Multiple-packet mode |
Bit 2 – DMAMODE DMA Mode
| Value | Description |
|---|---|
| 0 | DMA Mode 0 |
| 1 | DMA Mode 1 |
Bit 1 – SMX AHB Interrupt Mux Enable
| Value | Description |
|---|---|
| 0 | ACSR0 generates Multiple-packet mode; ACSR1 generates an INT1AHB interrupt |
| 1 | ACSR0 and ACSR1 generate an INT0AHB interrupt only |
Bit 0 – SCE Software Clear Enable
| Value | Description |
|---|---|
| 0 | Hardware clears interrupt after a ACSRn register read |
| 1 | Software writes a ‘1’ to clear |