30.10.26 AHB Channel Status 0 Register
The AHB Channel Status (ACSRn) registers contain interrupt bits for each of the 64 physical channels. When an ACSRn register bit is set, it indicates that the corresponding physical channel has an interrupt pending.
An AHB interrupt is triggered when either DNEn or ERRn is set within the AHB Channel Descriptor. The HC is notified of the channel interrupt via AHB interrupt Lines, when an interrupt occurs in ACSR0 (for channels 31 to 0) MediaLB interrupt INTFLAG. INT0AHB is set. When an interrupt occurs in ACSR1 (for channels 63 to 32) MediaLB interrupt INTFLAG. INT1AHB is set.
Interrupts in ACSR0 and ACSR1 can be optionally multiplexed onto a single interrupt signal, MediaLB INT0AHB interrupt, if ACTL.SMX = 1. If ACTL.SCE = 0, hardware automatically clears the interrupt bit(s) after the HC reads the ACSRn register. Alternatively, if ACTL.SCE = 1, software must write a 1 to the appropriate bit(s) of ACSRn to clear the interrupt(s).
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | ACSR0 |
| Offset: | 0x7D0 |
| Reset: | 0x00000000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| CHS [31:24] | |||||||||
| Access | R/W/HS/HC | R/W/HS/HC | R/W/HS/HC | R/W/HS/HC | R/W/HS/HC | R/W/HS/HC | R/W/HS/HC | R/W/HS/HC | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| CHS [23:16] | |||||||||
| Access | R/W/HS/HC | R/W/HS/HC | R/W/HS/HC | R/W/HS/HC | R/W/HS/HC | R/W/HS/HC | R/W/HS/HC | R/W/HS/HC | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| CHS [15:8] | |||||||||
| Access | R/W/HS/HC | R/W/HS/HC | R/W/HS/HC | R/W/HS/HC | R/W/HS/HC | R/W/HS/HC | R/W/HS/HC | R/W/HS/HC | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CHS [7:0] | |||||||||
| Access | R/W/HS/HC | R/W/HS/HC | R/W/HS/HC | R/W/HS/HC | R/W/HS/HC | R/W/HS/HC | R/W/HS/HC | R/W/HS/HC | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 31:0 – CHS [31:0] Bitwise Interrupt Status for Logical Channels [31:0]
Cleared by writing a 1.
CHS[n] = 1 indicates that an interrupt is pending on channel n.
If ACTL.SCE = 0, hardware automatically clears the interrupt bit(s) after the HC reads the ACSRn register. Alternatively, if ACTL.SCE = 1, software must write a 1 to the appropriate bit(s) of ACSRn to clear the interrupt(s).