30.10.27 AHB Channel Status 1 Register
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | ACSR1 |
| Offset: | 0x7D4 |
| Reset: | 0x00000000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| CHS[63:56] | |||||||||
| Access | R/W/HS/HC | R/W/HS/HC | R/W/HS/HC | R/W/HS/HC | R/W/HS/HC | R/W/HS/HC | R/W/HS/HC | R/W/HS/HC | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| CHS[55:48] | |||||||||
| Access | R/W/HS/HC | R/W/HS/HC | R/W/HS/HC | R/W/HS/HC | R/W/HS/HC | R/W/HS/HC | R/W/HS/HC | R/W/HS/HC | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| CHS[47:40] | |||||||||
| Access | R/W/HS/HC | R/W/HS/HC | R/W/HS/HC | R/W/HS/HC | R/W/HS/HC | R/W/HS/HC | R/W/HS/HC | R/W/HS/HC | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CHS[39:32] | |||||||||
| Access | R/W/HS/HC | R/W/HS/HC | R/W/HS/HC | R/W/HS/HC | R/W/HS/HC | R/W/HS/HC | R/W/HS/HC | R/W/HS/HC | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 31:0 – CHS[63:32] Bitwise Interrupt Status for Logical Channels [63:32]
Cleared by writing a 1.
CHS[n] = 1 indicates that an interrupt is pending on channel n.
If ACTL.SCE = 0, hardware automatically clears the interrupt bit(s) after the HC reads the ACSRn register. Alternatively, if ACTL.SCE = 1, software must write a 1 to the appropriate bit(s) of ACSRn to clear the interrupt(s).