35.6.7.9.7 Pointer Operation when DATA Reception

As in normal operation, when the first stop bit is received and a complete serial frame is present in the receive shift register, the contents of the shift register will be moved into the RX FIFO. Depending on the RX FIFO Threshold settings (CTRLC.RXTRHOLD), the Receive Complete interrupt flag (INTFLAG.RXC) is set, and the DATA can be read from RX FIFO. As long as data is present in RX FIFO (FIFOSPACE.RXSPACE ≠ 0), the CPU can read these data by accessing the DATA register. All pointers increment to their maximum value, dictated by the CTRLC.DATA32B bit, and then rolls over to ‘0’.

When both R Shifter and RX FIFO if enabled are full, the Buffer Overflow status bit is set (STATUS.BUFOVF) and optional ERROR interrupt is generated if enabled. The data will not be stored while BUFOVF is ‘1’, effectively pausing the module until software reads RX FIFO. While INTFLAG.RXC = 1 and STATUS.BUFOVF = 1, any subsequent incoming RX data will be lost.