1.3.2.2 64b6xb System Registers

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There are specific registers used for configuring the 64b6xb lane function options in the respective PolarFire Device Register Map or PolarFire SoC Register Map. Other fields are required to properly program the clocks, resets, XCVR, and lane overlay blocks and data path steering. System register field setting combinations is required for enabling 64b6xb lane usage.

Table 1-9. System Registers Affecting 64b6xb Data Path
Register Page xls	Register Name	Field Name	Description
pcslane	L64_R0	L64_CFG_BYPASS_GEARBOX	When = 1, both transmit and receive gearbox functions are bypassed.
		L64_CFG_BYPASS_SCRAMBLER	When = 1, both the scrambler and the descrambler are bypassed.
		L64_CFG_BYPASS_DISPARITY	Enable the Interlaken block disparity generation and checking blocks by setting cfg_bypass_disparity=0.
		L64_CFG_BYPASS_8B_MOD	When = 0 to obtain 64-bit fabric interfaces. Set cfg_bypass_8B_mode=1 for 32-bit fabric interfaces.
		L64_CFG_GRBX_64B67B	When = 1 for 67-bit blocks (Interlaken).
		L64_CFG_GRBX_SM_C49	When = 1 to enable IEEE 802.3 Clause 49 receiver lock state machine. Value of L64_CFG_GRBX_SM_C82 must be set as inverse of this bit.
		L64_CFG_GRBX_SM_C82	When = 1 to enable IEEE 802.2 Clause 82 receiver lock state machine behavior (40G link version). Value of L64_CFG_GRBX_SM_C49 must be set as inverse of this bit.
		L64_CFG_BER_MON_EN.	When = 1 to enable the BER Monitor in the receiver. The BER Monitor is useful in CPRI applications.
		L64_CFG_BER_1US_TIMER_VAL	This register must be set to the number of clock beats which most closely represents one microsecond. This field is used by the BER Monitor to time the 125 microsecond interval. Examples: CPRI rate 7A setting is 0x18B; CPRI rate 8 setting is 0x140; CPRI rate 9 setting is 0x107.