Simple Module Control Interface
(Ask a Question)| Port Name | Direction | Description |
|---|---|---|
| clock | IN | The input clock signal to the RTL module. |
| reset | IN | The input reset signal to the RTL module. |
| ready | OUT | Indicates the readiness of the RTL module. ready is set to 1 when the RTL module is ready to start a new iteration (invocation) with a new set of inputs. |
| start | IN | When ready is 1, setting start to 1 will start the execution of the RTL module; When ready is 0, the start signal is ignored by the RTL module. |
| finish | OUT | finish is set to 1 for one clock cycle when the RTL module finishes. |
| return_val | OUT | Holds the valid return value when finish is asserted. This signal does not exist if the top-level function has a void return type. |
Important:
- The top-level module starts a new iteration of execution upon the handshaking when both ready and start are high at a positive edge clock.
- For a circuit containing pipelined functions, the ready signal can be high before the previous invocations have finished, allowing multiple invocations to overlap and run in parallel.
- For circuits without pipelined functions, the ready signal is only asserted when the last invocation has finished.
- The scalar arguments (described in the next section) should be provided at the same time when the start signal is set to high.