1.3.5 DDR Interface

The DDR subsystems are hardened ASIC blocks for interfacing the LPDDR3, LPDDR4, DDR3, and DDR4 memories. It supports 16-bit, 32-bit, and 64-bit data bus width modes with ECC support. The DDRIO uses fixed impedance calibration for different drive strengths. These values are programmed using Libero SoC software for the selected I/O standard. The values are fed to the pull-up or pull-down reference network to match the impedance with an external resistor. For more information about DDR signals, see PolarFire FPGA and PolarFire SoC FPGA Memory Controller User Guide.