1.3.8 XCVR Interface

Important: PolarFire -CORE devices do not include transceiver functionality. Users must refer to the Unused Pin Recommendations provided in the Packaging Pin Assignment Table (PPAT) for information on transceiver-related pins and power supplies.

The transceiver I/O available in the PolarFire SoC devices are dedicated for high-speed serial communication protocols. Unused XCVR pin recommendations are detailed in the associated Package Pin assignment table at the following link: www.microchip.com/en-us/products/fpgas-and-plds/fpgas/polarfire-fpgas/polarfire-mid-range-fpgas#packaging. TX or RX pins do not have an internal pull-up.

For more information about unused conditions and power sequence, see PolarFire SoC FPGA Board Design Guidelines User Guide.

The following table lists the XCVR Interface pins and descriptions.

Table 1-9. XCVR Interface Pins
NameDirectionDescription
XCVR_xy_REFCLK_PInputDifferential serial reference clock.

xy - location

x - transceiver number (0, 1, 2, 3)

y - lane number (0, 1, 2, 3)

XCVR_xy_REFCLK_N
XCVR_x_TXy_POutputDifferential serial transmit pins.

x - transceiver number (0, 1, 2, 3)

y - lane number (0, 1, 2, 3)

XCVR_x_TXy_N
XCVR_x_RXy_PInputDifferential serial receive pins.

x - transceiver number (0, 1, 2, 3)

y - lane number (0, 1, 2, 3)

XCVR_x_RXy_N