1.3.7 Dedicated I/O Bank Pins

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JTAG, SPI, and DEVRST_N signals share the same Bank 3 supply and are not directly available to the fabric. SPI IOs are, however, dynamically switched over to be used by the fabric whenever the PolarFire SoC controller is not using them. Dedicated I/O bank supplies must be powered up higher than their operational threshold and enabled before the PolarFire SoC controller negates the main power-on reset to the fabric. Table 1-5, Table 1-6, and Table 1-7 list the JTAG, SPI, and DEVRST_N pin names and descriptions. Libero configures unused user I/O as input buffer disabled, and output buffer tri-stated with weak pull-up.

For more information about unused conditions and power sequence, see PolarFire SoC FPGA Board Design Guidelines User Guide.

The JTAG bank voltages can be set to operate at 1.8V, 2.5V, or 3.3V. The following table lists the JTAG pins.

Table 1-5. JTAG Pins
Pin Names	Direction	Weak Pull-Up/Unused Condition	Description
TMS	Input	Yes/DNC	JTAG test mode select
TRSTB	Input	Yes¹	JTAG test reset. Must be held low during device operation
TDI	Input	Yes/DNC	JTAG test data in In ATPG or Test mode, when using a 4-bit TDI bus, this I/O is used as TDI[0]
TCK	Input	No²	JTAG test clock
TDO	Output	No/DNC	JTAG test data out

Note: 1. If TRSTB is unused and in the Avionics mode, either an external 1 kW pull-down resistor must be connected to it, to override the weak internal pull-up or it must be driven low from the external source.

Note: 2. In unused condition, must be connected to VSS through 10 kW resistor.

Table 1-6. Device Reset Pins
Name	Direction	Weak Pull-up	Description
DEVRST_N	Input	22 kΩ	Device reset (asserted low)

Table 1-7. SPI Interface Pins
Name	Direction	Description
SCK	Bi-directional	SPI clock
SS	Bi-directional	SPI slave select
SDI	Input	SDI input for the shared SPI interface
SDO	Output	SDO output for the shared SPI interface
SPI_EN	Input	Pulled up or down through a resistor or driven dynamically from an external source to enable or tri-state the SPI I/O
IO_CFG_INTF	Input	Pulled up or down through a resistor or driven dynamically from an external source to indicate whether the shared SPI interface is a master or a slave. Dedicated to the system controller. 0: SPI slave interface 1: SPI master interface

Table 1-8. Special Pins
Name	Direction	Description
NC	—	No connect pin. This pin indicates that it is not connected within the circuitry. NC pins can be driven by any voltage or can be left floating with no effect on the operation of the device.
DNC	—	Do not connect pin. DNC pins must not be connected to any signal on the PCB, and they must be left unconnected.
LPRB_A	Output	Specifies an internal signal for probing (oscilloscope-like feature). The two live probe I/O cells function as either of the following: – Live probe – User I/O (HSIO)
LPRB_B	Output
FF_EXIT_N	Input	Reserved
Shield Signal	Output	Shield signal is required for each DDR data byte signal. It must be driven with maximum drive strength to improve the signal integrity.