18.6.4 UPLL Control


Bit	31	30	29	28	27	26	25	24
	UPLL_BYP				UPLLREFDIV[5:2]
Access	R/W/L				R/W/L	R/W/L	R/W/L	R/W/L
Reset	1				0	0	0	0


Bit	23	22	21	20	19	18	17	16
	UPLLREFDIV[1:0]		UPLLFBDIV[9:4]
Access	R/W/L	R/W/L	R/W/L	R/W/L	R/W/L	R/W/L	R/W/L	R/W/L
Reset	0	0	0	0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
	UPLLFBDIV[3:0]				UPLLRST	UPLLFLOCK	UPLLPOSTDIV1[5:4]
Access	R/W/L	R/W/L	R/W/L	R/W/L	R/W/L	R/W/L	R/W/L	R/W/L
Reset	0	0	0	0	1	0	0	0


Bit	7	6	5	4	3	2	1	0
	UPLLPOSTDIV1[3:0]				UPLLPWDN	UPLLBSWSEL[2:0]
Access	R/W/L	R/W/L	R/W/L	R/W/L	R/W/L	R/W/L	R/W/L	R/W/L
Reset	0	0	0	0	1	0	0	0

Bit 31 – UPLL_BYP UPLL Bypass

When this bit is set, the input clock REF bypasses PLL to PLLOUTx.

Note: It is recommended to setup SPLL first before setting up other PLLs, especially when using SYSPLL for generating main system clock.

Bits 27:22 – UPLLREFDIV[5:0] Reference Frequency Divide

Value	Description
1 ≤ UPLLDIVR ≤ 63	Divide by UPLLDIVR
0	Not used

Bits 21:12 – UPLLFBDIV[9:0] PLL Feedback Divider

Value	Description
16 ≤ UPLLFBDIV ≤ 1023	Divide by UPLLDIVR
0 to 15	Not used

Bit 11 – UPLLRST USB PLL Reset

Value	Description
1	Assert the reset to the UPLL
0	De-assert the reset to the UPLL

Bit 10 – UPLLFLOCK USB PLL Force Lock

Value	Description
1	Force the UPLL lock signal to be asserted
0	Do not force the UPLL lock signal to be asserted

Bits 9:4 – UPLLPOSTDIV1[5:0] First Post Divide Value

Value	Description
1 ≤ UPLLPOSTDIV1 ≤ 63,	Divide by UPLLPOSTDIV1
0	Not used

Bit 3 – UPLLPWDN PLL Power Down Register bit

Value	Description
1	PLL is powered down
0	PLL is active

Bits 2:0 – UPLLBSWSEL[2:0] PLL Bandwidth Select

Use the frequency range that matches the PLL closed loop bandwidth as based on the reference frequency divided by REFDIV to be set to allow the PLL loop filter to work with the post-reference divider frequency.

Name:	UPLLCON
Offset:	0xC
Reset:	0x00