18.6.5 EPLL Control


Bit	31	30	29	28	27	26	25	24
	EPLL_BYP			ECLKOUTEN	EPLLREFDIV[5:2]
Access	R/W/L			R/W/L	R/W/L	R/W/L	R/W/L	R/W/L
Reset	1			0	0	0	0	0


Bit	23	22	21	20	19	18	17	16
	EPLLREFDIV[1:0]		EPLLFBDIV[9:4]
Access	R/W/L	R/W/L	R/W/L	R/W/L	R/W/L	R/W/L	R/W/L	R/W/L
Reset	0	0	0	0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
	EPLLFBDIV[3:0]				EPLLRST	EPLLFLOCK	EPLLPOSTDIV1[5:4]
Access	R/W/L	R/W/L	R/W/L	R/W/L	R/W/L	R/W/L	R/W/L	R/W/L
Reset	0	0	0	0	1	0	0	0


Bit	7	6	5	4	3	2	1	0
	EPLLPOSTDIV1[3:0]				EPLLPWDN	EPLLBSWSEL[2:0]
Access	R/W/L	R/W/L	R/W/L	R/W/L	R/W/L	R/W/L	R/W/L	R/W/L
Reset	0	0	0	0	1	0	0	0

Bit 31 – EPLL_BYP EPLL Bypass

When this bit is set, the input clock REF bypasses PLL to PLLOUTx.

Note: It is recommended to setup SPLL first before setting up other PLLs, especially when using SYSPLL for generating main system clock.

Bit 28 – ECLKOUTEN Ethernet Clock Out pin Enable Bit

Value	Description
1	ETH_CLK_OUT Pin is enabled
0	ETH_CLK_OUT Pin is disabled

Bits 27:22 – EPLLREFDIV[5:0] Reference Frequency Divide

Value	Description
1 ≤ EPLLDIVR ≤ 63	Divide by EPLLDIVR
0	Not used

Bits 21:12 – EPLLFBDIV[9:0] PLL Feedback Divider

Value	Description
16 ≤ EPLLFBDIV ≤ 1023	Divide by EPLLDIVR
0 to 15	Not used

Bit 11 – EPLLRST EPLL Reset

Value	Description
1	Assert the reset to the EPLL
0	De-assert the reset to the EPLL

Bit 10 – EPLLFLOCK EPLL Force Lock

Value	Description
1	Force the EPLL lock signal to be asserted
0	Do not force the EPLL lock signal to be asserted

Bits 9:4 – EPLLPOSTDIV1[5:0] First Post Divide Value

Value	Description
1 ≤ EPLLPOSTDIV1 ≤ 63,	Divide by EPLLPOSTDIV1
0	Not used

Bit 3 – EPLLPWDN EPLL Power Down Register bit

Value	Description
1	EPLL is powered down
0	EPLL is active

Bits 2:0 – EPLLBSWSEL[2:0] PLL Bandwidth Select

Use the frequency range that matches the PLL closed loop bandwidth as based on the reference frequency divided by REFDIV to be set to allow the PLL loop filter to work with the post-reference divider frequency.

Name:	EPLLCON
Offset:	0x10
Reset:	0x00