18.6.15 User Clock Diagnostics Control
Note: The system unlock sequence must be done before this register can be
written.
| Name: | CLK_DIAG |
| Offset: | 0x78 |
| Reset: | 0x00000000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| NMICTR15 | NMICTR14 | NMICTR13 | NMICTR12 | NMICTR11 | NMICTR10 | NMICTR9 | NMICTR8 | ||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| NMICTR7 | NMICTR6 | NMICTR5 | NMICTR4 | NMICTR3 | NMICTR2 | NMICTR1 | NMICTR0 | ||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| UPLL_STOP | EPLL_STOP | SPLL1_STOP | LPRC_STOP | FRC_STOP | SOSC_STOP | POSC_STOP | |||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bits 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 – NMICTR Internal Value of Internal NMI Counter
Bit 6 – UPLL_STOP UPLL Clock Stop Control value
Note: This gating logic is outside
the CRU module.
| Value | Description |
|---|---|
| 0 | UPLL clock source runs as normal |
| 1 | UPLL clock source is stopped |
Bit 5 – EPLL_STOP EPLL Clock Stop Control value
Note: This gating logic is outside
the CRU module.
| Value | Description |
|---|---|
| 0 | EPLL clock source runs as normal |
| 1 | EPLL clock source is stopped |
Bit 4 – SPLL1_STOP SPLL Clock Stop Control value
Note: This gating logic is outside the CRU module.
| Value | Description |
|---|---|
| 0 | SPLL_CLK1 clock source runs as normal |
| 1 | SPLL_CLK1 clock source is stopped |
Bit 3 – LPRC_STOP LPRC Clock Stop Control value
Note: This gating logic is outside the CRU module.
| Value | Description |
|---|---|
| 0 | LPRC clock source runs as normal |
| 1 | LPRC clock source is stopped |
Bit 2 – FRC_STOP FRC Clock Stop Control value
Note: This gating logic is outside the CRU module.
| Value | Description |
|---|---|
| 0 | FRC clock source runs as normal |
| 1 | FRC clock source is stopped |
Bit 1 – SOSC_STOP SOSC Clock Stop Control value
Note: This gating logic is outside the CRU module.
| Value | Description |
|---|---|
| 0 | SOSC clock source runs as normal |
| 1 | SOSC clock source is stopped |
Bit 0 – POSC_STOP POSC Clock Stop Control value
Note: This gating logic is outside the CRU module.
| Value | Description |
|---|---|
| 0 | POSC clock source runs as normal |
| 1 | POSC clock source is stopped |