18.6.7 Reset Control Register

Note: When a Brown-Out Reset (BOR) occurs during Deep Sleep with ZPBOR enabled, RCON shows either ZPBOR only triggered or both ZBPOR and POR triggered.
Name: RCON
Offset: 0x18
Reset: 0x00000000
Property: -

Bit 3130292827262524 
 POR_IOPOR_CORE  BCFGERRBCFGFAILNVMLTANVMEOL 
Access R/W/HSR/W/HSR/W/HSR/W/HSR/W/HSR/W/HS 
Reset 000000 
Bit 2322212019181716 
       VBPORVBAT 
Access R/W/HSR/W/HS 
Reset 00 
Bit 15141312111098 
      DPSLPCMR  
Access R/W/HSR/W/HS 
Reset 00 
Bit 76543210 
 EXTRSWRDMTOWDTOSLEEPIDLEBORPOR 
Access R/W/HSR/W/HSR/W/HSR/W/HSR/W/HSR/W/HSR/W/HSR/W/HS 
Reset 00000000 

Bit 31 – POR_IO I/O Voltage POR Flag bit

  • 1 = A Power-on Reset has occurred due to I/O voltage.
  • 0 = A Power-on Reset has not occurred due to I/O voltage.

This bit is set by hardware at detection of an I/O POR event. User software must clear this bit to view the next detection.

Note: Writing 1 to this bit does not cause POR_IO reset.

Bit 30 – POR_CORE Core Voltage POR Flag bit

  • 1 = A Power-on Reset has occurred due to core voltage.
  • 0 = A Power-on Reset has not occurred due to core voltage.
This bit is set by hardware at detection of a core POR event. User software must clear this bit to view the next detection.
Note: Writing 1 to this bit does not cause POR_IO reset.

Bit 27 – BCFGERR BCFG Error Flag bit

  • 0 = A BCFG error has not occurred.
  • 1 = A BCFG error has occurred.

This bit is set when a primary BCFG value has an error but the secondary BCFG value is valid and used.

Bit 26 – BCFGFAIL BCFG Failure Flag bit

  • 0 = A BCFG failure has not occurred.
  • 1 = A BCFG failure has occurred.

This bit is set when both the Primary and Secondary BCFG values has an unrecoverable error. Only the default values are in effect.

Bit 25 – NVMLTA NVM Life Time Alert Flag bit

  • 0 = A NVM LTA error has not occurred.
  • 1 = A NVM LTA error has occurred.

This bit is set due to charge leakage, and the NVM (Flash) is nearing EOL.

Bit 24 – NVMEOL NVM End of Life Flag bit

  • 0 = A NVM EOL failure has not occurred.
  • 1 = A NVM EOL failure has occurred.

This bit may not be visible to the user because the part does not come out of Reset if the bit is asserted.

Bit 17 – VBPOR VBPOR Mode Flag bit

  • 1= A VBAT Domain POR has occurred.
  • 0 = A VBAT Domain POR has not occurred.
Note:
  • User may write this bit to 1. Does not cause a VBPOR event (used for testing only).
  • The actual register is not implemented as part of this module; bit location only reflects the state of the lpwr_vbpor_status input.

Bit 16 – VBAT VBAT Mode Flag bit

  • 1= A POR exit from VBAT has occurred. A true POR must be established with the valid VBAT voltage level on the VBAT pin.
  • 0 = A POR exit from VBAT has not occurred.

Bit 10 – DPSLP Deep Sleep Mode Flag bit

  • 1 = Deep Sleep mode has occurred.
  • 0 = Deep Sleep mode has not occurred.
This bit is set by hardware at the time of entry into the Deep Sleep mode. User software must clear this bit to view next detection.

Bit 9 – CMR Configuration Mismatch Reset Flag bit

  • 1 = A CMR event has occurred.
  • 0 = A CMR event has not occurred.
Note: Writing 1 to this bit does not cause Mismatch Reset.

Bit 7 – EXTR External Reset MCLR Status bit

  • 1 = A Master Clear (pin) Reset has occurred.
  • 0 = A Master Clear (pin) Reset has not occurred.
Note: Writing 1 to this bit does not cause a (MCLR).

Bit 6 – SWR Software Reset Flag bit

  • 1 = A SWR has occurred.
  • 0 = A SWR has not occurred.
Note: Writing 1 to this bit does not cause SWR.

Bit 5 – DMTO Deadman Timer Time-out Flag bit

  • 1 = DMT Time-out has occurred and caused a Reset.
  • 0 = DMT Time-out has not occurred.
Note: Writing ‘1’ to this bit does not cause DMT Reset.

Bit 4 – WDTO Watchdog Timer Time-Out Flag bit

  • 1 = WDT Time-out has occurred and caused a Reset.
  • 0 = WDT Time-out has not occurred.
Note: Writing ‘1’ to this bit does not cause WDTR.

Bit 3 – SLEEP Wake from Standby Sleep Flag bit

  • 1 = Device has been in Standby Sleep mode.
  • 0 = Device has not been in Standby Sleep mode.
Note: Writing 1 to this bit does not invoke the Standby Sleep mode.

Bit 2 – IDLE Wake from Idle Flag bit

  • 1 = Device was in Idle mode.
  • 0 = Device was not in Idle mode.
Note: Writing ‘1’ to this bit does not invoke the Idle mode.

Bit 1 – BOR BOR Flag bit

  • 1 = A BOR occurred.
  • 0 = A BOR did not occur.
This bit is set by hardware at detection of a BOR event. User software must clear this bit to view the next detection.
Note: Writing ‘1’ to this bit does not cause a BOR.

Bit 0 – POR POR Flag bit

  • 1 = A Power-on Reset occurred.
  • 0 = A Power-on Reset did not occur.
This bit is set by hardware at detection of a POR event. User software must clear this bit to view the next detection.
Note: Writing 1 to this bit does not cause a POR.