18.6.12 PBx Clock Divisor Control

Note: Perform the system unlock sequence before this register can be written. The Reset value for PB3DIV[6:0] is 0x09.

Name:	PBxDIV
Offset:	0x58 + (x-1)*0x04 [x=1..5]
Reset:	0x00008800


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16

Access
Reset


Bit	15	14	13	12	11	10	9	8
	PBxDIVON				PBxDIVRDY
Access	R				R
Reset	1				1


Bit	7	6	5	4	3	2	1	0
		PBxDIV[6:0]
Access		R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset		0	0	0	0	0	0	0

Bit 15 – PBxDIVON (x=1 to 5) Output Enable bit

Value	Description
1	Enables PBx Output clock
0	Disables PBx Output clock Note: Do not write PB1DIV.PB1DIVON bit as ‘`0`’, as the CRU system uses this clock, and it is one of the source for REFO.

Bit 11 – PBxDIVRDY (x=1 to 5) PBx Peripheral Clock Divisor Ready

Value	Description
1	Indicates the PB clock divisor logic is not switching divisors and the PBxDIV may be written.
0	Indicates the PB clock divisor logic is currently switching values and the PBxDIV cannot be written.

Bits 6:0 – PBxDIV[6:0] (x=1 to 5) PBx Peripheral Clock Divisor Control value

Value	Description
000_0000	Divide by 1 PBx Clock is same frequency as SYS_CLK
000_0001	Divide by 2 PBx Clock is 1/2 of SYS_CLK
000_0010	Divide by 3 PBx Clock is 1/3 of SYS_CLK
000_0011	Divide by 4 PBx Clock is 1/4 of SYS_CLK
...	...
...	...
000_1111	Divide by 16 PBx Clock is 1/16 of SYS_CLK
001_0000	Divide by 17 PBx Clock is 1/17 of SYS_CLK
...	...
...	...
111_1110	Divide by 127 PBx Clock is 1/127 of SYS_CLK
111_1111	Divide by 128 PBx Clock is 1/128 of SYS_CLK

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