18.6.1 CRU Oscillator Control
Note: Perform the system unlock sequence
before writing this register.
| Name: | OSCCON |
| Offset: | 0x00 |
| Reset: | 0x00200003 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| FRCDIV[2:0] | |||||||||
| Access | R/W/L | R/W/L | R/W/L | ||||||
| Reset | 0 | 0 | 0 | ||||||
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| DRMEN | 2SPDSLP | ||||||||
| Access | R/W/L | R/W/L | |||||||
| Reset | 0 | 1 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| COSC[3:0] | NOSC[3:0] | ||||||||
| Access | R | R | R | R | R/W/L | R/W/L | R/W/L | R/W/L | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CLKLOCK | SLPEN | CF | SOSCEN | OSWEN | |||||
| Access | R/W/L | R/W/L | R/W/HS/L | R/W/L | R/W/HC/L | ||||
| Reset | 0 | 0 | 0 | 1 | 1 |
Bits 26:24 – FRCDIV[2:0] Fast RC Clock Divider bits
| Value | Description |
|---|---|
| 000 | FRC is divided by 1 (default value) |
| 001 | FRC is divided by 2 |
| 010 | FRC is divided by 4 |
| 011 | FRC is divided by 8 |
| 100 | FRC is divided by 16 |
| 101 | FRC is divided by 32 |
| 110 | FRC is divided by 64 |
| 111 | FRC is divided by 256 |
Bit 23 – DRMEN Enable Dream Mode bit
| Value | Description |
|---|---|
| 1 | When
the SLEEP/WAIT (WFI) instruction is executed and SLPEN = 1,
DMA transfer complete causes the device to enter the Sleep
mode. |
| 0 | DMA transfer has no effect |
Bit 21 – 2SPDSLP 2-Speed start-up enabled in the Standby Sleep mode bit
Note: CFGCON2.WAKE2SPD specifies the
default Reset value.
| Value | Description |
|---|---|
| 1 | When the device exits the Standby Sleep mode, the SYS_CLK is going to be from FRC until the selected clock is ready. |
| 0 | When the device exits the Standby Sleep mode, the SYS_CLK is going to be from the selected clock. |
Bits 15:12 – COSC[3:0] Current Oscillator Selection bits (Read-only)
Note:
- Default value on reset is 4’b0000
- Loaded with NOSC[3:0] at the completion of a successful clock switch
- Set to FRC value (0000) when FSCM detects a failure and switches clock to FRC
| Value | Description |
|---|---|
| 0000 | Fast RC oscillator (FRC) divided by OSCCON.FRCDIV |
| 0001 | System PLL Clock-1 (SPLL_CLK1 module) (input clock is 128 MHz from RFPLL wrapper and divider set by SPLLCON) |
| 0010 | Primary Oscillator (POSC) |
| 0011 | Secondary Oscillator (SOSC) |
| 0100 | Low Power RC Oscillator (LPRC) |
| 0101 | Ethernet PLL Clock-2 (EPLL Module) (input clock and divider set by APLLCON) |
| 0110 | USB PLL Clock (UPLL Module) (input clock and divider set by UPLLCON) |
| 0111-1111 | Reserved for future use |
Bits 11:8 – NOSC[3:0] New Oscillator Selection bits
Note: Default value on reset is
4’b0000.
| Value | Description |
|---|---|
| 0000 | Fast RC oscillator (FRC) divided by OSCCON.FRCDIV |
| 0001 | System PLL Clock-1 (SPLL_CLK1 module) (input clock is 128 MHz from RFPLL wrapper and divider set by SPLLCON) |
| 0010 | Primary Oscillator (POSC) |
| 0011 | Secondary Oscillator (SOSC) |
| 0100 | Low-Power RC Oscillator (LPRC) |
| 0101 | Ethernet PLL Clock-2 (EPLL Module) (input clock and divider set by APLLCON) |
| 0110 | USB PLL Clock (UPLL Module) (input clock and divider set by UPLLCON) |
| 0111-1111 | Reserved for future use |
Bit 7 – CLKLOCK Clock Lock Enabled bit
Note:
- When set, this bit can only be cleared via a device Reset.
- When active, this bit prevents writes to the following registers: NOSC[3:0] and OSWEN.
| Value | Description |
|---|---|
| 1 | All
clock and PLL configuration registers are locked. These include OSCCON, OSCTRIM, SPLLCON, PBxDIV |
| 0 | Clock and PLL selection registers are not locked; configurations can be modified. |
Bit 4 – SLPEN Enable Sleep Mode bit
| Value | Description |
|---|---|
| 1 | When a WAIT Instruction is executed, the device enters the Standby Sleep mode. |
| 0 | When a WAIT instruction is executed, the device enters the IDLE mode. |
Bit 3 – CF Clock Fail Detect bit (Read/Writable/Clearable by application)
Note:
- Writing
‘
1’ to this bit initiates the clock-switching sequence by the clock switch state machine. - A Reset occurs when the clock switch state machine initiates a valid clock switching sequence.
- This bit is set when the clock fail event is detected.
| Value | Description |
|---|---|
| 1 | FSCM detected a clock failure |
| 0 | FSCM did not detected a clock failure |
Bit 1 – SOSCEN Low Power Secondary Oscillator Enable bit
Note: Set the value specified by the
SOSCEN configuration bits in CFGCON2.SOSCSEL on RESET.
| Value | Description |
|---|---|
| 1 | Enable Secondary Oscillator |
| 0 | Disable Secondary Oscillator |
Bit 0 – OSWEN Oscillator Switch Enable bit
Note:
- Writing
‘
0’ to this bit has no effect. - Hardware clears this bit after a successful clock switch.
- Hardware clears this bit after a redundant clock switch (NOSC = COSC).
- Hardware clears this bit after FSCM switches the oscillator to the fail-safe clock source.
| Value | Description |
|---|---|
| 1 | Requests the oscillator switch to select as specified by NOSC[3:0] bits |
| 0 | Oscillator switch is complete |