18.6.9 NMI Control Register

Note: The system unlock sequence must be done before writing this register. See System Configuration and Register Locking (CFG) from Related Links.

Name:	RNMICON
Offset:	0x20
Reset:	0x00000000
Property:	-


Bit	31	30	29	28	27	26	25	24
							DMTO	WDTR
Access							R/W	R/W
Reset							0	0


Bit	23	22	21	20	19	18	17	16
	SWNMI				EXT	PLVD	CF	WDTS
Access	R/W				R/W	R/W	R/W	R/W
Reset	0				0	0	0	0


Bit	15	14	13	12	11	10	9	8
	NMICNT[15:8]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	NMICNT[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bit 25 – DMTO Deadman Timer Time-Out Flag bit (this causes a Reset when NMICNT expires)

1 = DMT Time-out occurred and caused an NMI.
0 = DMT Time-out did not occur.

Note: Writing ‘1’ to this bit cause a user-initiated DMT NMI event and NMICNT start.

Bit 24 – WDTR Watchdog Timer Time-Out in Run Flag bit

1 = WDT Time-out occurred and caused an NMI (this may cause a Reset if NMICNT expires).
0 = WDT Time-out did not occur.

Note: Writing ‘1’ to this bit cause a user initiated WDT NMI event and NMICNT start.

Bit 23 – SWNMI Software NMI Trigger bit

1 = Writing ‘1’ to this bit generates an NMI.
0 = Writing ‘0’ to this bit has no effect.

Bit 19 – EXT External / Generic NMI Event bit

1 = A general NMI event was detected and caused an NMI.
0 = A general NMI event was not detected.

Note: Writing ‘1’ to this bit cause a user initiated EXT NMI event.

Bit 18 – PLVD Programmable Low Voltage Detect Event bit

1 = PLVD detected a low voltage condition and caused an NMI.
0 = PLVD did not detect a low voltage condition.

Note: Writing ‘1’ to this bit causes a user-initiated PLVD NMI event.

Bit 17 – CF Clock Fail Detect bit (Read/Clear-able by application)

1 = FSCM detected clock failure and caused an NMI.
0 = FSCM did not detect clock failure.

Note: Writing ‘1’ to this bit causes a user-initiated clock failure NMI event but does not cause a clock switch.

Bit 16 – WDTS Watch-Dog Timer Time-out in Standby Sleep Flag bit

1 = WDT Time-out occurred during the Standby Sleep mode and caused a wake-up from sleep.
0 = WDT Time-out did not occur during the Standby Sleep mode.

Note: Writing ‘1’ to this bit causes a user-initiated WDT NMI event.

Bits 15:0 – NMICNT[15:0] NMI Reset counter value bit

This bit field specifies the reload value used by the NMI Reset counter. The following events generate an NMI event and/or reset when the NMI_CNT expires on:

WDT event
DMT event


Values	Description
0x0000	No delay between NMI assertion and device Reset event.
0x0001	—
0x0002	—
.................	—
.................	—
.................	—
0xFFFE	—
0xFFFF	Number of SYSCLK cycles that the software has to clear the NMI event before a device Reset is performed. If the NMI event is cleared before the counter reaches zero, no device Reset is asserted.